Undervolting with CEP on – Ring Voltage keeping vcore up?

My rig:

• z790 Aorus Elite AX (rev1.0 – OnSemi NCP81530)
• 13700k
• (unrelated) H16A 7000 MT/s 32-42-42

Starting config, before the 0x129 microcode:

• Hyperthreading disabled
• x56 pcores, x43 ecores, x48 max ring
• 1.32v adaptive -20mV offset (1)
• 0.20 mOhms ACLL
• LOW LLC (0.75 mOhms impedance / 0.75 mOhms DC_LL)
• Working at about 1.24v under load

Trying the same configuration with CEP enabled, i was facing an issue… vcore wasn't dropping under load, no matter what adaptive offset i was using.

Basically, what i tried was:

• Enabling CEP / Intel defaults or "performance" settings (basically all the specs enforced)
• Setting MEDIUM LLC instead of LOW (from 0.75 mOhms to 0.62 mOhms)
• AC_LL to match the LLC impedance = DC_LL , so going from 0.20 mOhms to 0.62 mOhms.
• Tried adaptive vcore + offset but no matter what, even putting a -150mV offset, under load it was constantly working past 1.3v (vcore sensor). Since AC_LL wasn't a tool anymore, i was kind of lost.

Then, i tried to lower the ring voltage, the logic was to compensate for the increased AC_LL (going from 0.20 to 0.62 meant that under load, pulling 240A (arbitrary, really, but it sounds reasonable with a 307A iccmax), it was overvolting (0.62 mOhm – 0.20 mOhm) * 240A = ~100mV

So, i set a ring voltage offset of -100mV.

For the adaptive vcore offset, i started from the same -100mV and added another (0.75 mOhm – 0.62 mOhm) * 240A = ~30 mV to compensate for the increased LLC.

Then, considering my starting setup already had a -20mV offset, i added it on top aswell.

So, final results:

• RING : -100 mV offset from the increased AC_LL
• Adaptive vCore : -100 mV from the increased AC_LL , -30mV from the increased LLC , -20mV from the initial offset i was working with (1). So, -150mV total.

My questions are…

• Is what i did completely random or it makes any sort of sense? it works, but it might just be out of luck
• Is this expected behavior? I checked Buildzoid's youtube video about undervolting the 14900k with CEP enabled after the 0x129 microcode patch, and he didn't have to mess with the ring voltage AT ALL. Is this because i'm with HT off? Or because i manually changed the max ring clock? Or because it's a different motherboard (even if still gigabyte, but with onSemi) ? Or because… different VIDs table?

Anyway, i hope this can be useful for someone… kind of a weird journey.